uni/COMP2300/exam.tex

\documentclass[a4paper]{article}
\usepackage{layout}
\parindent0cm
\addtolength{\hoffset}{-2cm}
\addtolength{\voffset}{-2cm}
\setlength{\evensidemargin}{0cm}
\setlength{\marginparwidth}{0cm}
\setlength{\marginparsep}{0cm}
\setlength{\evensidemargin}{0cm}
\setlength{\oddsidemargin}{0cm}
\addtolength{\textwidth}{4cm}
\setlength{\footskip}{0cm}
\setlength{\headheight}{0cm}
\setlength{\headsep}{0cm}
\setlength{\topmargin}{0cm}
\addtolength{\textheight}{4cm}
\addtolength{\textwidth}{1cm}
\begin{document}
\begin{tabular}{|l|l|}
\hline
Operator & Associativity \\
\hline
() [] -$>$ . & left to right \\
! \~ ++ $--$ $-$ (type) \* \& sizeof & right to left \\
$\ast$ / \% & left to right \\
+ $-$ & left to right \\
$<<$ $>>$ & left to right \\
$<$ $<=$ $>$ $=>$ & left to right \\
== != & left to right \\
\& & left to right \\
\verb+^+ & left to right \\
$\mid$ & left to right \\
\&\& & left to right \\
$\mid\mid$ & left to right \\
?: & right to left \\
= += -= *= /= \%= $<<=$ $>>=$ \&= \verb+^+= $\mid$= & right to left \\
, & left to right \\
\hline
\end{tabular}


Von Neumann architecture: arithmetic-logic unit, control unit, memory,
connected by a bus.

Von Neumann machines perform the following steps:

\begin{enumerate}
\item Fetch the next instruction from memory at the address in the program
counter.
\item Add the length of the instruction to the program counter
\item Decode the instruction using the control unit.
\item Go back to step 1.
\end{enumerate}

ASCII characters of interest:
\begin{description}
\item[0-9] 48-57
\item[A-Z] 65-90
\item[a-z] 97-122
\end{description}

Note that there is a difference of 32 between `A' and `a', which corresponds
to toggling the 6th bit of a binary representation of the character's ASCII
value. Subtracting 48 from a ASCII character will yield it's numeric value,
i.e. `0' is 48, so $48-0=0$

Peanut registers

\begin{description}
\item[AC] The accumulator holds data during execution of the program, and is
always one of the sources as well as the destination of values computed by
arithmetic and logical instructions.
\item[CI] The current instruction register holds the instruction currently
being executed.
\item[SP] The stack pointer holds the address of the top of the stack
\item[XR] The index register holds the index (a memory address) used for
indexed instructions.
\item[PSW] The program status word contains 16 bits of status information
about the program. Many parts of the PSW have names of their own.
\end{description}

\texttt{
\begin{tabular}{ c c c c c c c c c c c c c c c c }
15 & 14 & 13 & 12 & 11 & 10 & 9 & & & & & & & & 0 \\
\hline 
\multicolumn{1}{|c|}{UN} & \multicolumn{1}{|c|}{UN} &
\multicolumn{1}{|c|}{EN} & \multicolumn{1}{|c|}{GT} &
\multicolumn{1}{|c|}{EQ} & \multicolumn{1}{|c|}{OV} & \multicolumn{9}{|c|}{PC} \\
\hline
\end{tabular}
}

As the program counter is 10 bits long, it can address up to 1024
instructions.\\

The Memory Address Register (MAR) holds the address of the current word being
fetched inside an instruction cycle, and the Memory Data Register (MDR)
holds the contents of that address.


Addressing modes

\begin{tabular}{|l|c|l|}
\hline
mode & symbol & meaning \\
\hline
immediate & \# & The numeric value, or ASCII value of a character provided is used \\
\hline
direct & none & The contents of the memory address provided is used \\
\hline
indirect & @ & The contents of the memory address stored at the memory
address provided is used \\
\hline
indexed & * & The contents of the memory address pointed at by the index
register is used, with the offset provided \\
\hline
stack & ! & The contents of the memory address pointed at by the stack
pointer is used, with the offset provided \\
\hline
\end{tabular}
\newpage
Task swapping

The program control block (PCB) contains:

\begin{itemize}
\item An ID number that identifies the process
\item Pointers to the locations in the program and its data where processing
last occurred
\item Register contents
\item States of various flags and switches
\item Pointers to the upper and lower bounds of the memory required for the
process
\item A list of files open by the process
\item The priority of the process
\item The status of all I/O devices needed by the process
\end{itemize}

Page replacement policies

\begin{itemize}
\item First in first out (FIFO)
\item Least recently used (LRU)
\item Last in first out (LIFO)
\item Least frequently used (LFU)
\end{itemize}

Negative and positive infinity (or NaN) are represented as an exponent of
all 1's and a significand of all 0's. Zero is represented as an exponent of
zero and a fraction of zero.

Big-endian architectures store the most significant byte at the lowest
address in the word, little-endian in the highest. Little-endian is a more
natural and consistent way to pick up 1, 2 and 4 or longer byte integers
(making multi-precision math easier). Big-endian allows for easy testing of
positive or negative numbers. Numbers store in order they are printed making
binary to decimal conversion easier.

\end{document}
1	\documentclass[a4paper]{article}
2	\usepackage{layout}
3	\parindent0cm
4	\addtolength{\hoffset}{-2cm}
5	\addtolength{\voffset}{-2cm}
6	\setlength{\evensidemargin}{0cm}
7	\setlength{\marginparwidth}{0cm}
8	\setlength{\marginparsep}{0cm}
9	\setlength{\evensidemargin}{0cm}
10	\setlength{\oddsidemargin}{0cm}
11	\addtolength{\textwidth}{4cm}
12	\setlength{\footskip}{0cm}
13	\setlength{\headheight}{0cm}
14	\setlength{\headsep}{0cm}
15	\setlength{\topmargin}{0cm}
16	\addtolength{\textheight}{4cm}
17	\addtolength{\textwidth}{1cm}
18	\begin{document}
19	\begin{tabular}{\|l\|l\|}
20	\hline
21	Operator & Associativity \\
22	\hline
23	() [] -$>$ . & left to right \\
24	! \~ ++ $--$ $-$ (type) \* \& sizeof & right to left \\
25	$\ast$ / \% & left to right \\
26	+ $-$ & left to right \\
27	$<<$ $>>$ & left to right \\
28	$<$ $<=$ $>$ $=>$ & left to right \\
29	== != & left to right \\
30	\& & left to right \\
31	\verb+^+ & left to right \\
32	$\mid$ & left to right \\
33	\&\& & left to right \\
34	$\mid\mid$ & left to right \\
35	?: & right to left \\
36	= += -= *= /= \%= $<<=$ $>>=$ \&= \verb+^+= $\mid$= & right to left \\
37	, & left to right \\
38	\hline
39	\end{tabular}
40
41
42	Von Neumann architecture: arithmetic-logic unit, control unit, memory,
43	connected by a bus.
44
45	Von Neumann machines perform the following steps:
46
47	\begin{enumerate}
48	\item Fetch the next instruction from memory at the address in the program
49	counter.
50	\item Add the length of the instruction to the program counter
51	\item Decode the instruction using the control unit.
52	\item Go back to step 1.
53	\end{enumerate}
54
55	ASCII characters of interest:
56	\begin{description}
57	\item[0-9] 48-57
58	\item[A-Z] 65-90
59	\item[a-z] 97-122
60	\end{description}
61
62	Note that there is a difference of 32 between `A' and `a', which corresponds
63	to toggling the 6th bit of a binary representation of the character's ASCII
64	value. Subtracting 48 from a ASCII character will yield it's numeric value,
65	i.e. `0' is 48, so $48-0=0$
66
67	Peanut registers
68
69	\begin{description}
70	\item[AC] The accumulator holds data during execution of the program, and is
71	always one of the sources as well as the destination of values computed by
72	arithmetic and logical instructions.
73	\item[CI] The current instruction register holds the instruction currently
74	being executed.
75	\item[SP] The stack pointer holds the address of the top of the stack
76	\item[XR] The index register holds the index (a memory address) used for
77	indexed instructions.
78	\item[PSW] The program status word contains 16 bits of status information
79	about the program. Many parts of the PSW have names of their own.
80	\end{description}
81
82	\texttt{
83	\begin{tabular}{ c c c c c c c c c c c c c c c c }
84	15 & 14 & 13 & 12 & 11 & 10 & 9 & & & & & & & & 0 \\
85	\hline
86	\multicolumn{1}{\|c\|}{UN} & \multicolumn{1}{\|c\|}{UN} &
87	\multicolumn{1}{\|c\|}{EN} & \multicolumn{1}{\|c\|}{GT} &
88	\multicolumn{1}{\|c\|}{EQ} & \multicolumn{1}{\|c\|}{OV} & \multicolumn{9}{\|c\|}{PC} \\
89	\hline
90	\end{tabular}
91	}
92
93	As the program counter is 10 bits long, it can address up to 1024
94	instructions.\\
95
96	The Memory Address Register (MAR) holds the address of the current word being
97	fetched inside an instruction cycle, and the Memory Data Register (MDR)
98	holds the contents of that address.
99
100
101	Addressing modes
102
103	\begin{tabular}{\|l\|c\|l\|}
104	\hline
105	mode & symbol & meaning \\
106	\hline
107	immediate & \# & The numeric value, or ASCII value of a character provided is used \\
108	\hline
109	direct & none & The contents of the memory address provided is used \\
110	\hline
111	indirect & @ & The contents of the memory address stored at the memory
112	address provided is used \\
113	\hline
114	indexed & * & The contents of the memory address pointed at by the index
115	register is used, with the offset provided \\
116	\hline
117	stack & ! & The contents of the memory address pointed at by the stack
118	pointer is used, with the offset provided \\
119	\hline
120	\end{tabular}
121	\newpage
122	Task swapping
123
124	The program control block (PCB) contains:
125
126	\begin{itemize}
127	\item An ID number that identifies the process
128	\item Pointers to the locations in the program and its data where processing
129	last occurred
130	\item Register contents
131	\item States of various flags and switches
132	\item Pointers to the upper and lower bounds of the memory required for the
133	process
134	\item A list of files open by the process
135	\item The priority of the process
136	\item The status of all I/O devices needed by the process
137	\end{itemize}
138
139	Page replacement policies
140
141	\begin{itemize}
142	\item First in first out (FIFO)
143	\item Least recently used (LRU)
144	\item Last in first out (LIFO)
145	\item Least frequently used (LFU)
146	\end{itemize}
147
148	Negative and positive infinity (or NaN) are represented as an exponent of
149	all 1's and a significand of all 0's. Zero is represented as an exponent of
150	zero and a fraction of zero.
151
152	Big-endian architectures store the most significant byte at the lowest
153	address in the word, little-endian in the highest. Little-endian is a more
154	natural and consistent way to pick up 1, 2 and 4 or longer byte integers
155	(making multi-precision math easier). Big-endian allows for easy testing of
156	positive or negative numbers. Numbers store in order they are printed making
157	binary to decimal conversion easier.
158
159	\end{document}